As is well known, electronic devices, in particular those integrated monolithically, if not carefully protected and sealed can be critically affected by the environmental conditions in which they are placed during assembly and/or during their lifetimes. In particular, the presence of humidity and other contaminating agents can result in the entry of undesired materials into the electrically active part of the device. This generally reduces the reliability of the device and can even irreversibly compromise its operation.
It is therefore crucial, especially for certain applications, to make the best possible provision for protection and sealing of the electrical circuit which is part of the device. For this purpose it is necessary to ensure perfect sealing also at the edge of the device.
For the meaning of edge of a device it should be remembered that a plurality of identical monolithically integrated circuits are formed simultaneously on a single wafer of semiconductor material, commonly monocrystalline silicon, in adjacent prepared areas. The individual devices are spaced and separated by unoccupied cross strips in which the surface of the silicon is left exposed. These strips are typically mutually orthogonal and are known as "scribe lines" and the wafer will be cut through them mechanically to separate the individual devices (the so-called "dicing" process). The edge of a device is thus the peripheral region thereof bordering on the associated scribe line.
After formation of the circuit electrical structures, i.e., of the electrical components, such as, for example, transistors or memory cells and their interconnections, the device is insulated and sealed. Layers of dielectric materials act as electrical and thermal insulators of the conducting interconnection layers and protect the underlying structures of the integrated circuit from mechanical stress such as impacts or from contaminants (impurities, moisture) by creating a barrier against those harmful substances coming from the environment.
The so-called final passivation includes a relatively thick layer completely covering the device to protect it. However, at the edge of the device the presence of the final passivation alone is not sufficient to ensure its sealing. Other measures are necessary. For this purpose primarily the most peripheral structures of the device are typically left inactive, i.e., disconnected electrically from the device terminals.
More specifically, for protection of the device at the edges there is formed a structure arranged peripherally which also permits sealing of the device. This is a device edge morphological structure and reference will be made thereto in the following description. It includes a closed ring completely surrounding the device along its entire periphery. This structure is known to those skilled in the art as Chip Outline Band (COB) i.e., a band surrounding the device.
The device edge morphological structure is formed simultaneously with the electrical structures of the integrated circuit. The more internal part of the COB, i.e., the part nearest the device, does indeed normally include structures which appear morphologically identical to the electrically active ones of the device. However, they do not have any electrical function since they are electrically insulated, but only act as termination for the device end. The COB structure is consequently different in different devices depending on the process used and the device design.
In any case the more external part of the COB, which terminates in the scribe line adjacent to and is contiguous with the preceding part, is designed so as to completely seal the device from the external environment. For this purpose there is applied the simple principle in accordance with which, to permit better sealing, each overlying layer must be terminated more externally than the one immediately below. The layers are disposed to virtually cover and enclose the previous layer. This way the edge descends gradually downward while going near the associated scribe line, such as to enclose the integrated circuit in subsequent shells, several times. An example of a device edge morphological structure of known type is shown in FIG. 1. Specifically there is represented in cross-section, not to scale, a peripheral portion of a single device. By way of example this is in particular a CMOS device, such as typically a memory circuit.
It is necessary to remember that in the more complex integrated circuits it is becoming ever more pressing to limit the area occupied by reducing the size of the components, and, thus, of the device to thereby increase the total number of devices which can be integrated on a single wafer. Accordingly, two or more interconnection levels are provided. It is in this framework that the present description is placed. The device to which reference is made by way of example in the figure comprises two interconnection levels.
In FIG. 1 the visible portion of the device edge morphological structure is indicated as a whole by reference number 1. Further to the right of the figure is seen a scribe line which is shown only partially and indicated by reference number 2, while to the left the device edge morphological structure 1 joins the active part of the device, i.e., the actual circuit (not shown in the figure). It should be remembered that the device edge morphological structure is shown in its most peripheral portion--in some cases another portion thereof comprising other electrically inactive structures could be present at the device periphery.
In FIG. 1 for greater clarity the COB is divided approximately and ideally in two regions as set forth above: a region indicated by reference number 3 placed more internally with respect to the circuit and comprising structures defining a sort of extension with continuity of the device circuit structures, and a region 4 which is more external or peripheral and has a device sealing function. The device is formed in a major surface 5 of a substrate 6 of monocrystalline silicon. The process calls for simultaneous formation of the circuit and its edge structure.
Once the structure of the electric circuit components (not shown in the figure) have been completed, a so-called "intermediate" dielectric layer acting as their insulation is formed above. In FIG. 1 can be seen the portion, indicated by reference number 7, of this layer which is included in the device edge morphological structure 1. Conventionally the intermediate dielectric comprises a Boron Phosphorus Silicon Glass (BPSG) layer, i.e., silicon oxide doped with boron and phosphorous. In the intermediate dielectric there are opened appropriate holes to the surface 5 of the substrate to allow contact therewith by overlying conducting levels.
A first interconnection level, i.e. a metallization layer, typically aluminum, more briefly known as "METAL 1", is overlaid on the intermediate dielectric 7. The first metallization layer, indicated by reference number 8, has portions in direct contact with the surface 5 through the above mentioned holes, denominated contacts, formed in the intermediate dielectric and not shown in the figure.
The metallization layer 8 is then patterned so as to have the appearance of metallic strips. As shown in FIG. 1, in this embodiment the METAL 1 in region 4 has a peripheral termination in contact with the surface 5 of the substrate 6. This peripheral termination is more external than the peripheral termination of the intermediate dielectric 7.
Over the first interconnection level 8 is formed a multilayer of dielectric material to insulate it from a subsequent second overlying metallization layer or briefly "METAL 2" indicated by reference number 9. In the description given below reference is made to this multilayer as to an intermetallization dielectric multilayer or intermetallization dielectric because it is placed between two metallization layers. The intermetallization dielectric is indicated as a whole by reference number 10 and also acts as a planarizer of the surface before formation of the second metallization layer 9 to ensure a deposition and a definition thereof without drawbacks.
As shown in FIG. 2 indeed, after formation of the METAL 1 layer, the resulting intermediate process structure displays zones with different heights. The intermediate process structure for this exemplified process is indicated as a whole by reference number 11 in the figure. It comprises the intermediate dielectric layer 7 and the first interconnection layer 8 already patterned. It can be observed from the figure that the free surface of the structure 11 displays considerable differences in height with a sort of stepped profile. This is true in general and to a different degree even in other process steps and typically is true for the intermediate structures created after deposition of each interconnection level.
As shown in FIG. 1, to planarize the surface of the structure 11, the overlying intermetallization dielectric 10 includes a layer of Spin-on Glass (SOG) which as known is commonly used for planarization in various steps of the formation of the integrated circuits. This is an amorphous material which is deposited in the fluid state, as a solution, by means of a "spinning" process, i.e., being sprayed over the entire surface of the wafer where it is deposited in such a manner as to fill the deepest zones and smooth the irregularities of the underlying structure. After hardening by evaporation of the solvent, a following anisotropic etching of the SOG leaves its top surface virtually planar, although a slight meniscus is formed because of the surface tension of the material. The etching is stopped when the relatively higher zones of the underlying structure are completely exposed.
It should be remembered, however, that the SOG, since it is a highly contaminating material because of its origin, must be enclosed between insulating layers so as not to come into contact with the active structures of the circuit. Specifically, as shown in FIG. 1, the intermetallization dielectric 10 hence includes a first layer comprising a silicon oxide, typically TEOS (tetraethylorthosilicate) indicated by 12, a layer of SOG 13 and a second layer of TEOS 14. The TEOS is chosen preferably because it has good chemical and physical characteristics and is a material which does not introduce contamination.
In accordance with the prior art process the first TEOS layer 12 is arranged conformal with the intermediate process structure 11 (FIG. 2) and accordingly displays a profile which is still not planar. Formation of SOG in accordance with what above mentioned so as to fill only the deepest portions, permits planarization of the surface. In this manner, after the conformal deposition of the second TEOS layer 14 there is obtained a virtually planar surface for deposition of the second interconnection level 9.
Following its formation, holes are opened in the intermetallization dielectric 10 by means of masking, these holes permitting formation of the so-called VIAs for contact between METAL 2 and METAL 1. As may be seen in the figure, in region 4 of the device edge morphological structure 1 the intermetallization dielectric 10 is terminated outside the termination of the first conducting layer 8, in accordance with the principle set forth above to ensure good sealing of the device. In accordance with a prior art technique, formation of the peripheral termination of the intermetallization dielectric multilayer takes place simultaneously with formation of the openings of the VIAs in the intermetallization dielectric 10, i.e., by using an opening in the same mask.
FIG. 1 shows a single VIA 15 in the region 3 of the edge morphological structure 1. The intermetallization dielectric 10 is, therefore, discontinuous since it is separated in two portions, one, indicated by reference number 10', being included in the region 3 and the other, shown by reference number 10", extending into both regions 3 and 4 of the morphological structure 1.
On this subject it should be remembered that formation both of the contacts, which allow connection between a metallic interconnection and the substrate or circuit components, and of the VIAs between conducting layers of different levels is very critical in very large scale integration manufacturing processes because of the extremely small cross-sectional dimensions which they must have and of the relatively great thickness of the dielectric layer through which the holes must be made. Under these conditions during sputtering deposition of the metallization layer which will form the contact the cover of the vertical walls of the "holes" becomes unsatisfactory and the metal deposited can display unacceptable thinning. On the other hand, it is not possible to reduce the thickness of the dielectric layer, and, hence, the depth of the contact proportionately to the cross-sectional dimensions. An approach commonly used includes using, for the metallization portion which is to be inside the holes, a metallic material, typically tungsten, titanium and/or titanium nitride, which can be deposited by chemical vapor phase deposition to allow easy filling of the hole.
In this direction there was developed a technique according to which the holes are first filled with tungsten plugs. The aluminum layer is then deposited so as to form the conducting layer. Techniques of this type are described, e.g., in the articles, "Selective CVD of tungsten and its applications to MOS VLSI" by Takahiko Moriya and Hitoshi Itoh, VLSI Research Center, Toshiba Co., presented at the Workshop 1985 of the Material Research Society; "A study of tungsten etchback for contact and VIA fill applications" by Jen-Jiang Lee and Dennis C. Hartman, presented at the IEEE VLSI Multilevel Interconnection Conference (VMIC), 1987.
More specifically, in accordance with a process to which specific reference is made in the following embodiments of the present invention, for the formation of the contacts and the VIAs in the holes there is first deposited a pre-adhesion or barrier layer. Typically the barrier layer comprises a first layer of titanium (Ti) on which is deposited a second layer of titanium nitride (TiN)(altogether Ti/TiN) for a total thickness varying between 50 nm and 90 nm. On the barrier layer a tungsten layer is then deposited by the CVD technique. A subsequent etching leaves the tungsten only in the holes in the form of plugs. This technique is described for example in European patent application no. 0543254 assigned to the assignee of the present invention. An improvement of this technique is described in European patent EP 0571691 also assigned to the present assignee.
In FIG. 1 the barrier layer Ti/TiN is indicated by reference number 16 and the tungsten plug by reference number 17. It is noted that, since the process calls for the peripheral termination of the intermetallization dielectric 10 to be obtained by means of a mask for formation of the VIAs, a tungsten residue is also present in the zone of the above mentioned termination. As may be seen in the figure, since an anisotropic etching is used, after partial removal of the tungsten for formation of the plugs a so-called tungsten bead, indicated by reference number 18, with an underlying very thin barrier layer (not shown), remains beside the above mentioned termination.
Like the first interconnection level 8, the second level 9 also terminates by contacting the surface 5 of the substrate more peripherally than the termination of the intermetallization dielectric multilayer. A relatively thick final passivation layer, indicated by reference number 19, completes formation of the device by providing protection of the circuit elements and the interconnection levels.
To allow separation of the devices provided on the same wafer the final passivation layer is then etched in the scribe line region, i.e., in region 2, until reaching the substrate surface 5. The scribe line has been formed at this stage. FIG. 1 shows the device as it appears at the termination of this step.
The process for formation of the device edge morphological structure 1 just described concomitantly with the electrical circuit formation process and illustrated in FIGS. 1 and 2 displays, however, some drawbacks which appear evident from an analysis of the obtained structure 1. It should be noted in fact that normally the SOG, in accordance with the conventional planarization process with three layers diagramed above, is completely enclosed between dielectric material layers. This is visible even in FIG. 1 in the region 3 of the device edge morphological structure, i.e., as concerns the intermetallization dielectric portion 10 placed more internally, to the left of the VIA 15.
However, as shown in FIG. 1, in accordance with the process for the formation of the device edge morphological structure in accordance with the prior art in the more external portion of the intermetallization dielectric multilayer 10 placed to the right of the VIA 15 and extending between the two regions 3 and 4, the SOG is not completely incorporated. Indeed, the intermetallization dielectric 10 in region 4 of the morphological structure 1 declines slowly in the direction of the device edge towards the surface 5 of the silicon until it reaches it. At the same time the SOG layer which as mentioned above forms a slight meniscus, is slowly thinned. The terminal etching of the intermetallization dielectric multilayer 10 immediately outside the termination of the first interconnection level 8 is performed in a zone where the thickness of the SOG layer 13 is not yet sufficiently reduced. Cutting of the multilayer 10 in accordance with the process described is performed far enough from the edge of the device so as to still permit formation further peripherally of the termination of the second interconnection level 9 in contact with the substrate. Accordingly the SOG terminal portion is not insulated from the second metallization layer 9, but instead is in contact with the tungsten bead 18.
The presence of SOG exposed to the next metallization layer 9 can give rise to a defects. In a certain percentage of devices there may in fact occur delayering of the overlying metallization level. As known to those skilled in the art, each SOG layer, if it has not been perfectly cured, shrinks before formation of the next metallization layer. The behavior of this material is due to a natural phenomenon known as outgassing. The problems of defects connected therewith when the outgassing occur at the interface with a metallization layer, as in our case, are illustrated for example in the article of C. Chiang, N. V. Lam, J. K. Chu, N. Cox, D. Fraser, J. Bozarth, B. Mumford, entitled "Defects study on spin on glass planarization technology", Proceedings Conference VMIC, 1987; and in the article of M. Kobayakawa, A. Arimatsu, F. Yokoyama, N. Hirashita, T. Ajioka, entitled "A study of outgassing from spin-on-glass films used for planarizing", Proceedings Conference VMIC, 1991. As analyzed in these articles the outgassing also leads to formation of structural defects in the metallic layers in direct contact with the SOG.
In addition, in the process just described and illustrated the presence of the tungsten bead in contact with the SOG enormously worsens the problem. As shown in FIG. 1 the SOG layer 13 when shrinking inwardly, before formation of the barrier layer Ti/TiN 16, leaves an empty space indicated by reference number 20 between the more external edges of the two dielectric layers 12 and 14. The side surface of the termination of the intermetallization dielectric 10, obtained after cutting of the dielectric and which must be covered by the second interconnection level, because of the SOG shrinkage, is accordingly irregular and with a negative slope.
This induces a stress in the barrier layer 16. To this is added the fact that the thickness of the barrier layer 16 is much reduced as described above and is deposited by an anisotropic technique, and, therefore, on such a negative step it is thinned, i.e., it does not have uniform thickness, and can even be missing at some points. For these reasons delayering of the barrier may occur, i.e., partial lifting thereof along the contact with the termination of the intermetallization dielectric.
The tungsten layer formed at this point is deposited both outside and inside the lifted edges of the barrier layer 16. It should be remembered that, during a common process for forming tungsten, tungsten fluoride is typically used as a source. This highly corrosive gas is able to penetrate any holes present in the barrier layer. Also the tungsten has high stress. The tungsten etching necessary for formation of the plugs thus generates a highly defective structure with holes. The following metallization layer 9 can accordingly be delayered, differently from how it appears in the ideal case shown in FIG. 1.
The device can be damaged in case of marked delayering in which there can be generated on the surface of the wafer residues of delaminated layers which cause short circuiting of active metallizations. The seriousness of the problem is on the other hand due to the fact that such a defective structure in the device edge morphological structure, which as such is not electrically active, may not immediately damage the functionality of the device. That is, the device in which this delayering phenomenon occurred at the terminal part of the METAL 2 would be functioning and would not fail upon testing. However, once operating it would become clearly unreliable in a more or less short time because it is not correctly sealed.
The problem described is accentuated in the devices located near the wafer edge, in which the barrier layer is thinned because it forms a meniscus upon deposition. A known attempt to solve this problem was given recently and is illustrated in FIG. 3. In this figure there is shown the same portion of the device edge morphological structure, here indicated by reference number 1', as in the preceding figure. The same reference numbers are kept for the same or equivalent structures and parts.
The approach includes modifying the etching masks of the VIAs, virtually avoiding opening a contact VIA in the intermetallization dielectric, whether in the more external region 4 of the device edge morphological structure or along the adjacent scribe line, for generating the peripheral termination of the layer. This means not etching the intermetallization dielectric in this zone as shown clearly in the figure. This avoids etching the SOG.
The layer of intermetallization dielectric 10 is accordingly as one might say extended to reach the region of the scribe line 2. It is etched away only during the following step of formation of the scribe line. This way the SOG layer 13 in the cutting region, i.e., the edge of the device in this case, is considerably thinned.
Differently from the case illustrated in the previous figure, the peripheral termination of the second interconnection level 9 is not in contact with the substrate as shown in FIG. 3. Anyway the second metallization layer 9 is removed in the zone adjacent to the scribe line 2 so that it is always isolated from the outside by means of the final passivation layer 19. The process just described accordingly allows obviating the problem of delayering of the METAL 2 at the bead, which is drastically eliminated. But this approach displays some drawbacks.
Although the intermetallization dielectric layer 10 is greatly extended and at the scribe line level where it is cut the SOG layer 13 is very thin, it is still necessary to point out that the latter is not completely absent. A small portion of SOG remains in contact with the outside. Since the SOG is hygroscopic because of its porosity there is the risk of moisture penetrating into the device with a resulting reliability problem.
Another problem is due to the structure obtained by means of this process. As may be readily seen, the dielectric layer on the scribe line before its etching is considerably increased with respect to the previous case shown in FIG. 1. Indeed, beyond the final passivation layer, on the scribe line there is also present the intermetallization dielectric 10. The total thickness, which can reach even 3 micron (.mu.m), can be excessive in the following terms. Primarily, excessive thickness extends the total time needed for completely etching the scribe line and makes necessary an overetching to completely clean the scribe line. Thus the entire process is delayed. This also implies greater complexity in controlling the process flow.
In addition, at the end of the etching it may happen that the scribe line is not well cleaned. There may remain residue of the oxide making up the lower layer to be etched, i.e., in this case the first dielectric layer of the intermetallization dielectric, in the most critical etching zones. These zones are typically those at the edges of the scribe line, and, in particular, at the feet of the opening which must be formed, i.e., where the etching arrives with more difficulty if the step is very steep. Other critical zones are those in which the corridor to be etched is very narrow, and, therefore, where the height-to-width ratio is very high. This happens, for example, in corridors at the sides of testing structures present in the center of the scribe line and which are not to be removed in this etching step. The presence of these oxide residues mainly near the scribe line crossings can generate mechanical damage to the contiguous devices during the dicing process. From this point there is a relatively high probability that crossing fracture lines will depart towards the adjacent devices. The devices involved are clearly not well sealed.
The problem illustrated accordingly seems almost insoluble. Indeed, good sealing is prevented for any device in which SOG is to be used as the planarization layer, because of the presence of at least one subsequent metallization level. The same problem arises both in the framework of a intermetallization dielectric for a device having at least two interconnection levels, and in the case not specifically described in which the SOG is already used in the intermediate dielectric for devices having a single metallization level and in which inside the intermediate dielectric there are to be formed contacts for the first metallization level.
It should be noted that although the drawbacks described are discussed for the case exemplified in FIGS. 1-3, they can appear every time a dielectric having similar characteristics, such as an amorphous planarizing material highly contaminating especially for the metallization layers and capable of generating defects, is used for the planarization instead of SOG. In addition these drawbacks are very devastating when the contacts and the VIAs are created by means of the described plug technique.